AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
MPR
1
rw1c
Magic Packet Received
Note:rw1c: Read only and Write one cleared.
1B
, Indicates AN985B/BX has received a magic packet. It is cleared
by write 1 or upon power-up reset. It is not affected by a hardware
or software reset
LSC
0
rw1c
Link Status Changed
Note:rw1c: Read only and Write one cleared.
1B
, Indicates AN985B/BX has detected a link status change event. It
is cleared by write 1 or upon power-up reset. It is not affected by a
hardware or software reset
CSR14, WPDR – Wake-up Pattern Data Register
All six wake-up patterns filtering information are programmed through WPDR register. The filtering information is
as follows:
Offset
0000h
0004h
0008h
000ch
0010h
0014h
0018h
001ch
0020h
0024h
0028h
002ch
0030h
0034h
0038h
003ch
0040h
0044h
0048h
004ch
0050h
0054h
0058h
005ch
0060h
31-24
23-16
15-8
7-0
Wake-up pattern 1 mask bits 31:0
Wake-up pattern 1 mask bits 63:32
Wake-up pattern 1 mask bits 95:64
Wake-up pattern 1 mask bits 127:96
CRC16 of pattern 1
Wake-up pattern 2 mask bits 31:0
Wake-up pattern 2 mask bits 63:32
Wake-up pattern 2 mask bits 95:64
Wake-up pattern 2 mask bits 127:96
CRC16 of pattern 2
Wake-up pattern 3 mask bits 31:0
Wake-up pattern 3 mask bits 63:32
Wake-up pattern 3 mask bits 95:64
Wake-up pattern 3 mask bits 127:96
CRC16 of pattern 3
Wake-up pattern 4 mask bits 31:0
Wake-up pattern 4 mask bits 63:32
Wake-up pattern 4 mask bits 95:64
Wake-up pattern 4 mask bits 127:96
CRC16 of pattern 4
Reserved
Reserved
Reserved
Reserved
Reserved
Wake-up pattern 1 offset
Wake-up pattern 2 offset
Wake-up pattern 3 offset
Wake-up pattern 4 offset
Wake-up pattern 5 mask bits 31:0
Wake-up pattern 5 mask bits 63:32
Wake-up pattern 5 mask bits 95:64
Wake-up pattern 5 mask bits 127:96
CRC16 of pattern 5
Wake-up pattern 5 offset
Rev. 1.51, 2005-11-30
1. CRC-16 polynomial: still pending
Data Sheet
64
INFINEON [ Infineon ]
