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AN985B/BX
Registers and Descriptors Description
2. Offset value is from 0-255 (8-bit width).
3. To load the whole wake-up frame-filtering information, consecutive 25 long words write operation to CSR14
should be done.
Watchdog Timer
WTMR_CSR15
Watchdog Timer
Offset
78H
Reset Value
0000 0000H
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5HV
UR
1-
6
6 5H
Field
Bits
Type
Description
CS
31
ro/ee16 Clock Save Mode
h[3]
0B
1B
, clock stuck at 0 when clock save mode enable
, clock stuck at 1 when clock save mode enable
CBS
RxS
30
29
28
ro/ee16 CARDBUS Save Mode
h[2] 1B , CARDBUS clock save mode enable
ro/ee16 Rx Save Mode
h[1] 1B , RX save mode enable
RxRe
ro/ee16 Rx Clock Reverse Mode
h[0]
ro
1B
, reverse (for NS HomePHY mode)
Res
RWR
27:6
5
Reserved
rw
Receive Watchdog Release
The time of release watchdog timer from last carrier deserted.
0B
1B
, 24 bit-time
, 48 bit-time
RWD
4
rw
Receive Watchdog Disable
0B
, If the receiving packet’s length is longer than 2560 bytes the
watchdog timer will be expired
1B
, disable the receive watchdog
Res
JCLK
3
2
ro
rw
Reserved
Jabber Clock
0B
1B
, cut off transmission after 2.6 ms (100 Mbit/s) or 26 ms (10 Mbit/s)
, cut off transmission after 2560 byte-time
NJ
1
0
rw
rw
Non-Jabber
0B
, if jabber expired re-enable transmit function after 42 ms
(100 Mbit/s) or 420 ms (10 Mbit/s)
, immediately re-enable the transmit function after jabber expired
1B
JBD
Jabber Disable
1B , disable transmit jabber function
Data Sheet
65
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
