AN985B/BX
Registers and Descriptors Description
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
5HV
UR
ꢉ ꢀ ꢃ ꢁ ꢂ
5H &5:3:3:3:3:3
V &7 ꢀ( ꢁ( ꢂ( ꢃ( ꢄ(
/L /L
Qꢅ Qꢅ
:)03 /6
5( 5( &(
:)03 /6
5 5 &
5HV
UR
5HV
UR
UR UZ UZ UZ UZ UZ UZ
UZ UZ
UZ UZ UZ
UZꢁUFZꢁUFZꢁF
Field
Res
Bits
31
Type
ro
Description
Reserved
CRCT
30
rw
CRC-16 Type
0B
1B
, Initial contents = 0000h
, Initial contents = FFFFh
WP1E
WP2E
WP3E
WP4E
WP5E
Res
29
28
27
26
25
24:18
17
rw
rw
rw
rw
rw
ro
Wake-up Pattern n Matched Enable
n = 1 to 5
Reserved
Link Off Detect Enable
LinkOFF
rw
The AN985B/BX will set the LSC bit of CSR13 after it has detected that
link status is from ON to OFF.
LinkON
16
rw
Link On Detect Enable
The AN985B/BX will set the LSC bit of CSR13 after it has detected that
link status is from OFF to ON.
Res
WFRE
15:11
10
ro
rw
Reserved
Wake-up Frame Received Enable
The AN985B/BX will include the “Wake-up Frame Received” event into
wake-up events. If this bit is set, AN985B/BX will assert PMES bit of
PMR1 after AN985B/BX has received a matched wake-up frame.
MPRE
LSCE
9
8
rw
rw
Magic Packet Received Enable
The AN985B/BX will include the “Magic Packet Received” event into
wake-up events. If this bit is set, AN985B/BX will assert PMES bit of
PMR1 after AN985B/BX has received a Magic packet.
Link Status Changed Enable
The AN985B/BX will include the “Link Status Changed” event into wake-
up events. If this bit is set, AN985B/BX will assert PMES bit of PMR1 after
AN985B/BX has detected a link status changed event.
Res
WFR
7:3
2
ro
rw1c
Reserved
Wake-up Frame Received
Note:rw1c: Read only and Write one cleared.
1B
, Indicates AN985B/BX has received a wake-up frame. It is cleared
by write 1 or upon power-up reset. It is not affected by a hardware
or software reset
Data Sheet
63
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
