AN985B/BX
Registers and Descriptors Description
Lost Packet Counter
LPC_CSR8
Lost Packet Counter
Offset
40H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
/3
5HV
/3&
&2
UR
URꢊOK
URꢊOK
Field
Res
LPCO
Bits
31:17
16
Type
ro
ro/lh
Description
Reserved
Lost Packet Counter Overflow
Note:LH = High Latching and cleared by writing 1
1B , while lost packet counter overflowed. Cleared after read
Lost Packet Counter
Increment the counter while packet discarded since there was no host
receives descriptors available. Cleared after read.
LPC
15:0
ro/lh
Note:LH = High Latching and cleared by writing 1
Serial Port Register
SPR_CSR9
Serial Port Register
Offset
48H
Reset Value
0004 000EH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
5HV
UR
ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
0'000'0'5H 656:5H 65
6' 6' 6& 6&
, /. 6
5HV
,
& 2 &
V
& &
V
6
2
UR
UZ UZ UZ UZ UR UZ UZ UR UZ
UR UZ UZ UZ
Field
Res
Bits
31:20
Type
ro
Description
Reserved
MDI
19
rw
MII Management Data Input
Specified read data from the external PHY
MMC
MDO
18
17
rw
rw
MII Management Control
0B
1B
, Write operation to the external PHY
, Read operation from the external PHY
MII Management Data Output
Specified Write Data to the external PHY
Data Sheet
61
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
