AN985B/BX
Registers and Descriptors Description
IER_CSR7
Interrupt Enable Register
Offset
38H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
1, $, 5H )% 5H *3 5H5:56585& 78 5H 7- 7' 73 7&
V (ꢀ V 7ꢀ V 7ꢀ ,( ,( ,( ,( V 7ꢀ 8ꢀ 6ꢀ ,(
5HV
UR
(
(
UZ UZ UR UZ UR UZ UR UZ UZ UZ UZ UZ UR UZ UZ UZ UZ
Field
Res
NIE
Bits
31:17
16
Type
ro
rw
Description
Reserved
Normal Interrupt Enable
1B , enable all the normal interrupt bits (see bit16 of CSR5)
Abnormal Interrupt Enable
1B , enable all the abnormal interrupt bits (see bit15 of CSR5)
AIE
15
rw
Res
FBEIE
14
13
ro
rw
Reserved
Fatal Bus Error Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable fatal bus error
interrupt
Res
GPTIE
12
11
ro
rw
Reserved
General Purpose Timer Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable general-purpose
timer expired interrupt
Res
RWTIE
10
9
ro
rw
Reserved
Receive Watchdog Time-out Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable receive watchdog
time-out interrupt
RSIE
RUIE
RCIE
TUIE
8
7
6
5
rw
rw
rw
rw
Receive Stopped Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable receive stopped
interrupt
Receive Descriptor Unavailable Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable receive descriptor
unavailable interrupt
Receive Completed Interrupt Enable
1B
, combine this bit and bit 16 of CSR7 to enable receive completed
interrupt
Transmit Under-flow Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable transmit under-flow
interrupt
Res
TJTTIE
4
3
ro
rw
Reserved
Transmit Jabber Timer Time-out Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable transmit jabber timer
time-out interrupt
TDUIE
2
rw
Transmit Descriptor Unavailable Interrupt Enable
1B
, combine this bit and bit 16 of CSR7 to enable transmit descriptor
unavailable interrupt
Data Sheet
59
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
