AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
OM
11:10
rw**
Operating Mode
Note:w** = only write when the transmit and receive processor both
stopped.
00B , normal
01B , MAC loop-back
10B , reserved
11B , reserved
Res
MM
9:8
7
ro
rw***
Reserved
Multicast Mode
Note:w*** = only write when the receive processor stopped.
1B
, receive all multicast packets
PR
6
5
rw***
rw**
Promiscuous Mode
Note:w*** = only write when the receive processor stopped.
0B
1B
, receive only the right destination address packets
, receive any good packet
SBC
Stop Back-off Counter
Note:w** = only write when the transmit and receive processor both
stopped.
0B
1B
, back-off counter is not effected by carrier
, back-off counter stop when carrier is active and resume when
carrier drop.
Res
PB
4
3
ro
rw***
Reserved
Pass Bad Packet
Note:w*** = only write when the receive processor stopped.
0B
1B
, filters all bad packets
, receives any packets if pass address filter, including runt packets,
CRC error, truncated packets... For receiving all bad packets, the
bit 6 of CSR6 should be set to 1.
PU
SR
2
1
rw***
rw
Pass Unicast Mode
Note:w*** = only write when the receive processor stopped.
1B
, back-off counter stop when carrier is active and resume when
carrier drop.
Start/Stop Receive
0B , receive processor will enter stop state after the current reception
frame completed. This value is effective only when the receive
processor is in the running or suspending state. Notice: In “Stop
Receive” state the PAUSE packet and Remote Wake Up packet
won’t be affected and can be received if the corresponding function
is enabled.
1B
, receive processor will enter running state
Res
0
ro
Reserved
Interrupt Enable Register
Data Sheet
58
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
