UZꢊ UR UZꢊ
UZꢊ UZUZꢊꢊ UZꢊꢊ
UR UZꢊꢊU
ZꢊꢊUꢊZꢊꢊ URUZꢊꢊUZꢊꢊꢊUZ UR
AN985B/BX
Registers and Descriptors Description
Network Access Register
NAR_CSR6
Network Access Register
Offset
30H
Reset Value
0008 0040H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢃ
ꢁ
ꢂ
5H 64
6% 5H
5H
V
5HV
UR
6)
5HV
UR
75 67 )& 20 5HV 0035
3% 38 65
V
(
& V
Field
Res
SF
Bits
31:22
21
Type
ro
rw*
Description
Reserved
Store and Forward for Transmit
Note:w* = only write when the transmit processor stopped.
0B
1B
, disable
, enable ignore the transmit threshold setting
Res
SQE
20
19
ro
rw*
Reserved
SQE Disable
Note:w* = only write when the transmit processor stopped.
0B
, enable SQE function for 10BASE-T operation. The AN985B/BX
provides SQE test function for 10BASE-T half duplex operation
, disable SQE function
1B
Res
TR
18:16
15:14
ro
rw*
Reserved
Transmit Threshold Control
Note:w* = only write when the transmit processor stopped.
00B , 128-byte (100 Mbit/s) 72-byte (10 Mbit/s)
01B , 256-byte (100 Mbit/s) 96-byte (10 Mbit/s)
10B , 512-byte (100 Mbit/s) 128-byte (10 Mbit/s)
00B , 1024-byte (100 Mbit/s) 160 -byte (10 Mbit/s)
ST
FC
13
12
rw
Stop Transmit
0B
1B
, stop (default)
, start
rw**
Force Collision Mode
Note:w** = only write when the transmit and receive processor both
stopped.
0B
1B
, disable
, generate collision when transmit (for test in loop-back mode)
Data Sheet
57
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
