IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH BUSY(3)
t
WP
R/W
L
tWB
BUSY
R
(1)
tWH
R/W
R
(2)
2692 drw 12
NOTES:
1. tWH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
(1)
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING
ADDR
ADDRESSES MATCH
'A' and 'B'
CE'B'
(2)
t
APS
CE'A'
t
BAC
tBDC
BUSY'A'
2692 drw 13
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING (1)
t
RC or tWC
ADDR'A'
ADDR'B'
BUSY'B'
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
t
APS
tBAA
tBDA
2692 drw 14
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).
6.02
9
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
