IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S = VIH)(2,4,5)
tWC
MATCH
ADDR"A"
tWP
R/
W"A"
tDW
tDH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBAA
tBDA
tBDD
BUSY"B"
tWDD
VALID
DATAOUT "B"
(3)
tDDD
3199 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL (refer to Chip Enable Truth Table).
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/ "A"
W
(3)
tWB
BUSY"B"
(1)
tWH
.
R/
W"B"
(2)
3199 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the "Slave" version.
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
