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IDT7027S25PF 参数 Datasheet PDF下载

IDT7027S25PF图片预览
型号: IDT7027S25PF
PDF下载: 下载PDF文件 查看货源
内容描述: 高速32K ×16的双端口静态RAM [HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 19 页 / 161 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT7027S/L  
High-Speed 32K x 16 Dual-Port Static RAM  
Military, Industrial and Commercial Temperature Ranges  
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)  
tWC  
ADDRESS  
(7)  
tHZ  
OE  
tAW  
CE SEM (9,10)  
or  
UB or LB(9)  
(3)  
(2)  
(6)  
tWR  
tAS  
tWP  
R/W  
DATAOUT  
DATAIN  
(7)  
tOW  
tWZ  
(4)  
(4)  
tDW  
tDH  
3199 drw 07  
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)  
tWC  
ADDRESS  
tAW  
(9,10)  
or  
CE SEM  
(6)  
tAS  
(3)  
(2)  
tWR  
tEW  
(9)  
or  
UB LB  
R/  
W
tDW  
tDH  
DATAIN  
3199 drw 08  
NOTES:  
1. R/W or CE or UB and LB = VIH during all address transitions.  
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.  
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.  
4. During this period, the I/O pins are in the output state and input signals must not be applied.  
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.  
6. Timing depends on which enable signal is asserted last, CE or R/W.  
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure  
2).  
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be  
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the  
specified tWP.  
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.  
10. Refer to Chip Enable Truth Table.  
10  
6.42