IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating TemperatureandSupply VoltageRange(6,7)
7027X20
Com'l Only
7027X25
Com'l, Ind.
& Military
7027X35
Com'l &
Military
7027X55
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S=VIH)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
20
20
20
20
20
20
20
20
20
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
17
17
20
35
____
____
____
____
5
5
5
5
BUSY Disable to Valid Data(3)
____
____
____
____
30
30
35
40
Write Hold After BUSY(5)
15
17
25
25
____
____
____
____
BUSY TIMING (M/S=VIL)
BUSY Input to Write(4)
Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
____
____
____
____
____
____
____
____
tWB
0
0
0
0
ns
ns
tWH
15
17
25
25
____
____
____
____
____
____
____
____
45
30
50
35
60
45
80
65
ns
ns
3199 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
12
6.42
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
