IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table V
Address Bus Arbitration(4)
Inputs
Outputs
AOL-A14L
OR-A14R
(1)
(1)
A
Function
Normal
Normal
Normal
Write
CE
L
CER
X
BUSYL
BUSYR
X
H
X
NO MATCH
MATCH
H
H
H
H
H
H
X
H
MATCH
L
L
MATCH
(2)
(2)
(3)
Inhibit
3199 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7027 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of the actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of the actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
Truth Table VI Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
3199 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7027.
2. There are eight semaphore flags written to via I/O0 and read from all the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL, to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
FunctionalDescription
TheIDT7027providestwoportswithseparatecontrol,addressand
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
inmemory.TheIDT7027hasanautomaticpowerdownfeaturecontrolled
by CE0 and CE1. The CE0 and CE1 control the on-chip power down
circuitrythatpermitstherespectiveporttogointoastandbymodewhen
not selected (CE = VIH). When a port is enabled, access to the entire
memoryarrayispermitted.
(INTL) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as CER = R/WR = VIL per Truth Table
IV. The leftportclears the interruptthroughaccess ofaddress location
7FFEwhenCEL=OEL=VIL,R/Wisa"don'tcare".Likewise,therightport
interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation
7FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustread
the memory location 7FFF. The message (16 bits) at 7FFE or 7FFF is
user-defined since it is an addressable SRAM location. If the interrupt
functionisnotused,addresslocations7FFEand7FFFarenotusedas
mail-boxes by ignoring the interrupt, but as part of the random access
memory.RefertoTruthTableIVfortheinterruptoperation.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)is assignedtoeachport. Theleftportinterruptflag
16
6.42
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