IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tOH
tSAA
VALID ADDRESS
VALID ADDRESS
tACE
A0-A2
tWR
tAW
tEW
SEM
tSOP
tDW
DATAIN
VALID
DATAOUT
VALID(2)
I/O0
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
3199 drw 09
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table.
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2)
"A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
3199 drw 10
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
11
6.42
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
