IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupteddataintheslave.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse anyBUSYindicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.Ifthewriteinhibitfunctionofbusylogicisnot
desirable,theBUSYlogiccanbedisabledbyplacingthepartinslavemode
withtheM/Spin.OnceinslavemodetheBUSYpinoperatessolelyasa
writeinhibitinputpin.Normaloperationcanbeprogrammedbytyingthe
BUSY pins HIGH. If desired, unintended write operations can be pre-
ventedtoa portbytyingthe BUSYpinforthatportLOW.
Semaphores
TheIDT7027isafastDual-Port32Kx16CMOSStaticRAMwithan
additional8addresslocationsdedicatedtobinarysemaphoreflags.These
flagsalloweitherprocessorontheleftorrightsideoftheDual-PortSRAM
toclaimaprivilegeovertheotherprocessorforfunctionsdefinedbythe
systemdesigner’ssoftware.Asanexample,thesemaphorecanbeused
byoneprocessortoinhibittheotherfromaccessingaportionoftheDual-
Port SRAM or any other shared resource.
TheDual-PortSRAMfeaturesafastaccesstime,andbothportsare
completelyindependentofeachother.Thismeansthattheactivityonthe
leftportinnowayslows theaccess timeoftherightport.Bothports are
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
haveanautomaticpower-downfeaturecontrolledbyCE theDual-Port
SRAMenable,andSEM,thesemaphoreenable.TheCEandSEMpins
controlon-chippowerdowncircuitrythatpermitstherespectiveporttogo
intostandbymodewhennotselected. Thisistheconditionwhichisshown
in Truth Table II where CE and SEM = VIH.
TheBUSYoutputsontheIDT7027RAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
A15
CE0
CE0
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSYR
BUSYR
BUSYL
BUSYL
SystemswhichcanbestusetheIDT7027containmultipleprocessors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit
from a performance increase offered by the IDT7027's hardware
semaphores, which provide a lockout mechanism without requiring
complexprogramming.
CE1
CE1
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSYR
BUSYR
BUSYR
BUSYL
BUSYL
BUSYL
3199 drw 17
Softwarehandshakingbetweenprocessors offers themaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations.TheIDT7027doesnotuseitssemaphoreflagstocontrol
anyresourcesthroughhardware,thusallowingthesystemdesignertotal
flexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin
either processor. This can prove to be a major advantage in very high-
speedsystems.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7027 RAMs.
Width Expansion with Busy Logic
Master/SlaveArrays
WhenexpandinganIDT7027RAMarrayinwidthwhileusingBUSY
logic, one master part is used to decide which side of the RAM array
willreceiveaBUSYindication,andtooutputthatindication.Anynumber
ofslavestobeaddressedinthesameaddressrangeasthemaster,use
theBUSYsignalasawriteinhibitsignal.ThusontheIDT7027RAMthe
BUSYpinisanoutputifthepartisusedasaMaster(M/Spin=VIH),and
theBUSYpinisaninputifthepartusedasaSlave(M/Spin=VIL)asshown
in Figure 3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. Itignores whetheranaccess is a readorwrite. In
a master/slave array, bothaddress andchipenable mustbe validlong
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortSRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
that semaphore’s status or remove its request for that semaphore to
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
