IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1,5)
tWC
(2)
ADDR"A"
INTERRUPT SET ADDRESS
(4)
(3)
tAS
tWR
"A"
CE
R/
W"A"
(3)
tINS
INT"B"
3199 drw 15
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
(3)
tAS
"B"
CE
"B"
OE
(3)
tINR
INT"B"
3199 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See the Interrupt Truth Table IV.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
Truth Table IV Interrupt Flag(1,4)
Left Port
Right Port
WL
R/
WR
R/
A14L-A0L
7FFF
X
A14R-A0R
X
Function
CEL
L
OEL
X
INTL
X
CER
X
OER
X
INT
R
(2)
L
X
X
X
X
X
L
L
Set Right INT Flag
R
(3)
X
X
X
L
L
7FFF
7FFE
X
H
Reset Right INT Flag
R
(3)
X
X
X
L
L
X
X
Set Left INT Flag
L
(2)
L
L
7FFE
H
X
X
X
X
Reset Left INT Flag
L
3199 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. Refer to Chip Enable Truth Table.
15
6.42
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
