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IDT7027S25PF 参数 Datasheet PDF下载

IDT7027S25PF图片预览
型号: IDT7027S25PF
PDF下载: 下载PDF文件 查看货源
内容描述: 高速32K ×16的双端口静态RAM [HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 19 页 / 161 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT7027S/L  
High-Speed 32K x 16 Dual-Port Static RAM  
Military, Industrial and Commercial Temperature Ranges  
5V 5V  
AC Test Conditions  
dInput Pulse Levels  
GND to 3.0V  
5ns Max.  
1.5V  
893  
893  
Input Rise/Fall Times  
DATAOUT  
BUSY  
INT  
DATAOUT  
Input Timing Reference Levels  
Output Reference Levels  
Output Load  
30pF  
5pF*  
1.5V  
347  
347Ω  
Figures 1 and 2  
3199 drw 04  
3199 tbl 11  
Figure 2. Output Test Load  
(for tLZ, tHZ, tWZ, tOW)  
Figure 1. AC Output Test Load  
*Including scope and jig.  
AC Electrical Characteristics Over the  
OperatingTemperatureandSupplyVoltageRanges(4,6)  
7027X20  
Com'l Only  
7027X25  
Com'l, Ind.  
& Military  
7027X35  
Com'l &  
Military  
7027X55  
Com'l &  
Military  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max. Unit  
READ CYCLE  
____  
____  
____  
____  
tRC  
Read Cycle Time  
20  
25  
35  
55  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
____  
____  
____  
____  
tAA  
Address Access Time  
20  
20  
20  
25  
25  
25  
35  
35  
35  
55  
55  
55  
Chip Enable Access Time(3)  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
tACE  
tABE  
Byte Enable Access Time(3)  
AOE  
t
Output Enable Access Time  
12  
13  
20  
30  
____  
____  
____  
____  
tOH  
tLZ  
Output Hold from Address Change  
Output Low-Z Time(1,2)  
3
3
3
3
____  
____  
____  
____  
3
3
3
3
Output High-Z Time(1,2)  
12  
15  
15  
25  
____  
____  
____  
____  
HZ  
t
tPU  
tPD  
Chip Enable to Power Up Time(2,5)  
Chip Disable to Power Down Time(2,5)  
Semaphore Flag Update Pulse (OE or SEM)  
Semaphore Address Access Time  
0
0
0
0
____  
____  
____  
____  
____  
____  
____  
____  
20  
25  
35  
50  
____  
____  
____  
____  
SOP  
t
10  
12  
15  
15  
____  
____  
____  
____  
tSAA  
20  
25  
35  
55  
ns  
3199 tbl 12  
NOTES:.  
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).  
2. This parameter is guaranteed by device characterization, but is not production tested.  
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.  
4. 'X' in part numbers indicates power rating (S or L).  
5. Refer to Chip Enable Truth Table.  
6. Industrial temperature: for other speeds, packages and powers contact your sales office.  
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