ICS1531 参数 Datasheet PDF下载

型号：	ICS1531
PDF下载：	下载PDF文件查看货源
内容描述：	888位MSPS A / D转换器与行同步时钟发生器 [Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator]
分类和应用：	转换器时钟发生器
文件页数/大小：	76 页 / 525 K
品牌：	ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]

ICS1531 Data Sheet - Preliminary

Chapter 6 Register Set

6.5.32 Register 30h: ADC CTRL

The ADC CTRL (Analog-to-Digital Converter Control) Register is used to control the ADC.

Table 6-31. ADC CTRL Register

Bit

Bit Name

Bit Definition

Ac- Spec.

cess Func.

Re-

set

30:7

ADC_OE

Analog-to-Digital Converter (Digital) Outputs Enable.

R/W

–

^T•^his⁰^b⁼^it^T^e^hⁿ^e^ab^A^l^D^esCth^d^e^ig^A^ita^D^l^C^ou^d^tⁱ^p^g^u^it^t^a^s^l^a^o^r^u^e^tp^d^u^is^ts^a^.^bled.

(The ICS1531 output pads are high-impedance.)

• ^{1 = The ADC digital outputs are enabled.}

(The polarity is controlled by Reg 30:5.)

30:6

ADC_Sel

Analog-to-Digital Converter (Capture) Select.

R/W

–

^T•^his⁰^b⁼^{it selects a mode for the ADC.}

– The clock rate is 2 pixels per clock (half-rate clock).

– Both the ‘A’ and ‘B’ channels each provide 24-bit pixels

(48 bits total).

• ^{1 =}

– The clock rate is 1 pixel per clock (full-rate clock).

– The ‘A’ channel provides 24-bit pixels (24 bits total).

– The ‘B’ channel is driven either high or low, depending

on the value of Reg 30:5 (ADC_INV).

30:5

30:4

ADC_Inv

Analog-to-Digital Converter (Output) Invert (Disable).

R/W

–

^T•^his⁰^b⁼^it^T^d^h^is^e^a^A^bl^D^e^C^{s t}^o^h^uetp^inuv^t^esr^a^s^r^io^eⁿ^inov^f^e^t^r^h^t^e^ed^A^.^{DC outputs.}

• ^{1 = The ADC outputs are not inverted (default).}

Force_ADC

Force Analog-to-Digital Converter (Outputs).

^T•^his⁰^b⁼^it^N^fo^o^r^r^c^m^e^a^slt^o^o^p^‘o^e^f^r^f^a^’^t^a^io^llⁿ^{output buffers for the ADC pin.}

• ^{1 = Force all ADC output buffers low or high as follows:}

– Reg 30:5 = 0 to force buffers low

– Reg 30:5 = 1 to force buffers high

30:3

30:2

CLAMP_Pol

CLAMP_Sel

Clamp Polarity.

R/W

–

^T•^his⁰^b⁼^it^T^s^h^e^e^le^p^c^o^ts^la^t^r^h^it^e^y^p^o^o^f^l^t^a^h^r^e^ity^si^o^g^fⁿ^t^a^h^leto^si^a^gn^c^a^la^l^m^to^p^a^is^cl^p^a^o^m^s^p^it^.^ive.

• ^{1 = The polarity of the signal to a clamp is negative.}

Clamp (Source) Select.

^T•^his⁰^b⁼^it^T^s^h^e^e^le^s^c^o^ts^ur^th^ce^e^o^so^f^u^th^r^e^ce^si^o^g^fⁿ^t^a^h^l^e^is^siⁱ^gⁿⁿ^te^a^r^lⁿ^t^aoll^a^y^c^g^l^e^aⁿ^m^e^p^{ra. ted.}

• ^{1 = The source of the signal is from the CLAMP pin.}

^V•^ide⁰^o⁼^A^V^m^id^p^e^l^o^if^a^ie^m^r^p^D^liⁱ^f^s^ie^a^r^bⁱ^l^s^e^e^.^{nabled (default).}

30:1

30:0

VA_Disable

FA_Disable

–

• ^{1 = Video amplifier is disabled to conserve power.}

^F•^ine⁰^A⁼^d^T^j^h^u^e^st^D^D^Aⁱ^C^sa^s^b^a^l^r^e^e^.^{enabled and they drive the VRTR,}

R/W

VRTG, and VRTB pins internally.

• ^{1 = The DACs are disabled and the VRTR, VRTG, and}

VRTB pins must be driven externally with ADC top

reference voltage.

ICS1531 Rev N 12/1/99

December, 1999

电子百科

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