ICS1531 参数 Datasheet PDF下载

型号：	ICS1531
PDF下载：	下载PDF文件查看货源
内容描述：	888位MSPS A / D转换器与行同步时钟发生器 [Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator]
分类和应用：	转换器时钟发生器
文件页数/大小：	76 页 / 525 K
品牌：	ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]

ICS1531 Data Sheet - Preliminary

Chapter 6 Register Set

6.5.29 Register 2Ch: OUTPUT MUX

The OUTPUT MUX Register is used to select the source for the REF pin and STATUS pin (an active-low

pin formerly called ‘LOCK’).

Table 6-29 refers to ADC_FUNC, an internally generated signal that is delayed so it is in the same domain

as the internal ADC_CLK signal. Functionally, depending on the setting of Reg 06:3, ADC_FUNC is

equivalent to either ADCSYNC (which provides recovered HSYNC) or the input HSYNC.

Table 6-29. OUTPUT MUX Register

Bit

Bit Name

Bit Definition

Ac- Spec. Re-

cess Func.

set

2C:7

High_Drive

High Drive.

–

This bit selects a drive strength for all analog-to-digital

converter outputs.

• ^{0 = Drive strength is normal strength.}

• ^{1 = Drive strength is doubled.}

^O•^ut⁰^pu⁼^t^D^E^isⁿ^a^a^b^b^l^l^e^e^O^fo^S^r^C^O^O^S^U^C^T^O^o^U^u^T^tp^.^ut.

• ^{1 = Enable OSCOUT output.}

OSCOUT (Multiplexer) Select [1-0].

These bits select the output from a 4-way multiplexer (MUX) to

the OSCOUT pin.

2C:6

OE_OSC

R/W

–

2C:5-

2C:4

OSC_Sel [1-0]

• ^{0 = The OSCOUT source is OSC.}

• ^{1 = The OSCOUT source is OSC/2.}

• ^{2 = The OSCOUT source is OSCDIVIDER.}

• ^{3 = The OSCOUT source is a reserved value.}

^R•^es^S^e^e^rv^e^e^S^d^e^.^{ction 6.1, “Reserved Bits”.}

• ^{This bit must be programmed to ‘0’.}

2C:3

2C:2

Reserved

REF_Sel

–

REF (Status) Select.

R/W

^T•^his⁰^b⁼^it^Tshee^le^R^c^E^ts^F^th^o^e^ut^R^pu^E^t^F^so^p^uⁱⁿ^rc^r^eefi^esr^f^e^rⁿ^o^c^m^e^t^o^h^uetⁱ^pⁿ^u^ptu^a^t^s^to^fo^th^ll^e^ow^p^s^ix^:^{el PLL}

PDINPUT (the Phase/Frequency Detector Input).

• ^{1 = The REF output source is from ADC_FUNC. (For more}

information on ADC_FUNC, see Section 6.5.7, “Register

06h: Output Enables”.)

2C:1-

2C:0

LCKSEL [1-0]

(PLL) Lock (Status) Select [1-0].

These bits select the lock status output for the active-low

R/W

–

^S•^TA⁰^T⁼^US^Th^p^eⁱⁿ^lo^(f^c^o^k^rm^st^e^a^r^t^l^u^y^s^c^o^a^u^ll^t^epd^ut^‘L^is^O^f^C^o^K^r^’^t^.^{h)e pixel PLL.}

• ^{1 = The lock status output is for the Dynamic Phase Adjust.}

• ^{2 = The lock status output is for PNLCLK.}

• ^{3 = The lock status output is for MCLK.}

ICS1531 Rev N 12/1/99

December, 1999

电子百科

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