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ICS1531 参数 Datasheet PDF下载

ICS1531图片预览
型号: ICS1531
PDF下载: 下载PDF文件 查看货源
内容描述: 888位MSPS A / D转换器与行同步时钟发生器 [Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator]
分类和应用: 转换器时钟发生器
文件页数/大小: 76 页 / 525 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS1531 Data Sheet - Preliminary  
Chapter 6 Register Set  
6.5.25 Register 28h: MCLK-SS0  
The MCLK-SS0 (MCLK Spread-Spectrum Counter 0) Register is used in combination with the MCLK-SS1  
Register to specify the amount of clock spread. (To select values, see Section 7.3, “Programming Spread  
Spectrum”.)  
Table 6-25. MCLK-SS0 Register  
Bit  
Bit Name  
Bit Definition  
Ac- Spec.  
cess Func.  
Re-  
set  
28:7- MCLK_SS0 [7-0] MCLK Spread-Spectrum (Counter) 0 [7-0].  
R/W  
D-MK  
0
28:0  
These bits are the least-significant bits [7-0] for the MCLK  
spread-spectrum counter.  
6.5.26 Register 29h: MCLK-SS1  
The MCLK-SS1 (MCLK Spread-Spectrum Counter 1) Register is used in combination with the MCLK-SS0  
Register. (To select values, see Section 7.3, “Programming Spread Spectrum”.)  
Table 6-26. MCLK-SS1 Register  
Bit  
Bit Name  
Bit Definition  
Ac- Spec.  
cess Func.  
Re-  
set  
ResSeerveeSde.ction 6.1, “Reserved Bits”.  
These bits can be programmed to ‘0’.  
29:7- Reserved  
29:4  
0
29:3- MCLK_SS1 [3-0] MCLK Spread-Spectrum (Counter) 1 [3-0].  
R/W  
D-MK  
0
29:0  
These bits are the most-significant bits [11-8] for the MCLK  
spread-spectrum counter.  
ICS1531 Rev N 12/1/99  
December, 1999  
Copyright © 1999, Integrated Circuit Systems, Inc.  
All rights reserved.  
43  
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