欢迎访问ic37.com |
会员登录 免费注册
发布采购

ICS1531 参数 Datasheet PDF下载

ICS1531图片预览
型号: ICS1531
PDF下载: 下载PDF文件 查看货源
内容描述: 888位MSPS A / D转换器与行同步时钟发生器 [Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator]
分类和应用: 转换器时钟发生器
文件页数/大小: 76 页 / 525 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
 浏览型号ICS1531的Datasheet PDF文件第35页浏览型号ICS1531的Datasheet PDF文件第36页浏览型号ICS1531的Datasheet PDF文件第37页浏览型号ICS1531的Datasheet PDF文件第38页浏览型号ICS1531的Datasheet PDF文件第40页浏览型号ICS1531的Datasheet PDF文件第41页浏览型号ICS1531的Datasheet PDF文件第42页浏览型号ICS1531的Datasheet PDF文件第43页  
ICS1531 Data Sheet - Preliminary  
Chapter 6 Register Set  
6.5.19 Register 22h: PNLCLK-SS0  
The PNLCLK-SS0 (PNLCLK Spread-Spectrum Counter 0) Register is used in combination with the  
PNLCLK-SS1 Register to specify the amount of clock spread. (To select values, see Section 7.3,  
“Programming Spread Spectrum”.)  
Table 6-19. PNLCLK-SS0 Register  
Bit  
Bit Name  
Bit Definition  
Ac- Spec.  
cess Func.  
Re-  
set  
22:7- PNLCLK_SS0  
22:0 [7-0]  
PNLCLK Spread-Spectrum (Counter) 0 [7-0].  
These bits are the least-significant bits [7-0] for the PNLCLK  
spread-spectrum counter.  
R/W  
D-PK  
0
6.5.20 Register 23h: PNLCLK-SS1  
The PNLCLK-SS1 (PNLCLK Spread-Spectrum Counter 1) Register is used in combination with the  
PNLCLK-SS0 Register. (To select values, see Section 7.3, “Programming Spread Spectrum”.)  
Table 6-20. PNLCLK-SS1 Register  
Bit  
Bit Name  
Bit Definition  
Ac- Spec.  
cess Func.  
Re-  
set  
ResSeerveeSde.ction 6.1, “Reserved Bits”.  
These bits can be programmed to ‘0’.  
23:7- Reserved  
23:4  
0
23:3- PNLCLK_SS1  
PNLCLK Spread-Spectrum (Counter) 1 [3-0].  
These bits are the most-significant bits [11-8] for the PNLCLK  
spread-spectrum counter.  
R/W  
D-PK  
0
23:0  
[3-0]  
ICS1531 Rev N 12/1/99  
December, 1999  
Copyright © 1999, Integrated Circuit Systems, Inc.  
All rights reserved.  
39  
 复制成功!