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ICS1531 参数 Datasheet PDF下载

ICS1531图片预览
型号: ICS1531
PDF下载: 下载PDF文件 查看货源
内容描述: 888位MSPS A / D转换器与行同步时钟发生器 [Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator]
分类和应用: 转换器时钟发生器
文件页数/大小: 76 页 / 525 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS1531 Data Sheet - Preliminary  
Chapter 6 Register Set  
6.5.15 Register 12h: Rd_Reg  
The Rd_Reg (Read Register) is used to read the lock status of the four PLLs on the ICS1531.  
Table 6-16. Rd_Reg Register  
Bit  
Bit Name  
Bit Definition  
Ac- Spec. Re-  
cess Func.  
set  
12:7- Reserved  
12:4  
Reserved.  
Read  
N/A  
BecTahuesseethbeitssecbaintsnoatreberepardo-gornalmy:med.  
Information on these bits can be ignored.  
PNL0C=LTKhLeoPcNkL(CSLtaKtuiss)u. nlocked’.  
12:3  
12:2  
12:1  
12:0  
PNLCLK_Lock  
Read  
Read  
Read  
Read  
N/A  
N/A  
N/A  
N/A  
1 = The PNLCLK is ‘locked’.  
MCLK_Lock  
Pixel PLL_Lock  
DPA_Lock  
MCLK Lock (Status).  
0 = The MCLK is ‘unlocked’.  
1 = The MCLK is ‘locked’.  
Pixe0l=PThhaesep-iLxoelcPkeLdL iLsouonploLcokcekd’(.Status).  
1 = The pixel PLL is ‘locked’.  
Dyn0a=mTichePhDaPsAeiAsdujunlsotcLkeodck. (Status).  
1 = The DPA is ‘locked’.  
6.5.16 Register 13h-1Fh: Reserved  
These registers are reserved. (See Section 6.1, “Reserved Bits”.)  
ICS1531 Rev N 12/1/99  
December, 1999  
Copyright © 1999, Integrated Circuit Systems, Inc.  
All rights reserved.  
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