ICS1531 参数 Datasheet PDF下载

型号：	ICS1531
PDF下载：	下载PDF文件查看货源
内容描述：	888位MSPS A / D转换器与行同步时钟发生器 [Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator]
分类和应用：	转换器时钟发生器
文件页数/大小：	76 页 / 525 K
品牌：	ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]

ICS1531 Data Sheet - Preliminary

Chapter 6 Register Set

6.5.7 Register 06h: Output Enables

The Output Enables Register is used to select and enable various outputs.

Note: Table 6-10 refers to ADC_FUNC, an internally generated signal that is delayed so it is in the same

domain as the internal ADC_CLK signal (that is, the pixel clock). Functionally, depending on the

setting of Reg 06:3, ADC_FUNC is equivalent to either ADCSYNC (which provides recovered

HSYNC) or the input HSYNC.

Table 6-10. Output Enables Register

Bit

Bit Name

Bit Definition

Ac- Spec. Re-

cess Func.

set

^R•^es^S^e^e^rv^e^e^S^d^e^.^{ction 6.1, “Reserved Bits”.}

• ^{This bit can be programmed to ‘0’.}

06:7 Reserved

06:6 OE_Tck

–

Output Enable Clock.

–

^T•^his⁰^b⁼^it^T^e^hⁿ^e^ab^pli^e^x^selth^cl^e^oc^p^k^ix^o^e^u^l^t^c^p^lo^u^c^t^k^is^o^d^uⁱ^t^spaub^t^le^o^dⁿ⁽^t^h^hⁱ^e^gh^C^-^Lⁱ^K^mp^p^eⁱⁿ^d^.^ance).

• ^{1 = The pixel clock output is enabled.}

06:5 OE_ADCRCLK

Output Enable for ADCRCLK.

–

^T•^his⁰^b⁼^it^T^e^hⁿ^e^ab^fo^le^ll^s^ow^thⁱⁿ^e^g^cl^a^o^r^c^e^k^b^oou^t^t^h^pu^tr^tuf^e^{o:r ADCRCLK. When this bit is:}

– The clock output for the ADC is disabled (that is, high-

impedance).

– Because the clock source for the ADC is accepted from

the ADCRCLK pin, an external clock can be provided to

the ADC.

• ^{1 = The following are both true:}

– The clock output for the ADC is enabled.

– The input multiplexer selects the internal pixel clock.

06:4 OE_ADCSYNC Output Enable for ADCSYNC.

R/W

–

^T•^his⁰^b⁼^it^T^e^hⁿ^e^ab^fo^le^ll^s^ow^thⁱⁿ^e^g^o^a^u^r^t^e^pu^b^t^o^f^t^ohr^t^A^ru^D^e^C^:^{SYNC. When this bit is:}

– The output for the ADCSYNC signal is disabled (high-

impedance).

– An external sync signal for the ADC is accepted from the

ADCSYNC pin.

• ^{1 = The following are both true:}

– The output for the ADCSYNC signal is enabled.

– The input multiplexer selects the internal sync signal.

06:3 FUNC_Sel

FUNC Select.

–

This bit selects the source of the signal to ADC_FUNC. (See the

ⁿ•^ote⁰^a⁼^t^T^thhe^e^f^s^ir^o^s^u^t^r^o^c^f^e^th^isisr^t^eacbo^le^{ve.)red HSYNC.}

• ^{1 = The source is REF, the input HYSNC signal that is}

conditioned before it goes to the phase-locked loop block.

ICS1531 Rev N 12/1/99

December, 1999

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