iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 23/30
SCLK
SDAT
a4
a3
a2
a1
a0
d7
d6
d1
d0
0
0
0
0
1
5 bit address
8 bit data
SDAT is sampled on
falling edge of SCLK
SDAT is externally driven
extra clocks before
new access
00 indicates write
new access
Figure 13: Register bank write access on 2W-Interface
On a register read access the register content is data bit d(7) returned on SDAT. This clock cycle is used
shifted out on SDAT. A read access is indicated by to avoid any bus contention while turning around the
SDAT 10 after the start bit. There is an idle clock re- bus driver.
quired between the last address bit a(0) and the first
SCLK
SDAT
a4
a3
a2
a1
a0
d7
d6
d0
1
0
0
0
1
5 bit address
8 bit data
SDAT is sampled on
falling edge of SCLK
SDAT is externally driven
SDAT is driven by iC-TW2
10 indicates read
extra clocks before
new access
new access
Figure 14: Register bank read access on 2-wire interface
Write access to the EEPROM follows the procedure is 0100 which performs an erase followed by a write
depicted in Figure 15. A start bit is followed by four therefore allowing the user to write a new value to the
command bits c-1-e-b. The encoding of the command EEPROM with only one interface access.
bits is shown in Table 31. The most useful command
SCLK
SDAT
c
e
b
a2
a1
a0
d31
d30
d1
d0
0
0
1
1
20
ms
3 bit address
32 bit data
SDAT is sampled on
falling edge of SCLK
SDAT is externally driven
command select erase control block operation
wait for at least 20ms
before any new access
extra clocks before
new access
Figure 15: EEPROM write access on 2-wire interface
ICHAUS [ IC-HAUS GMBH ]
