iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 21/30
START UP
power supply
ramp-up
reset
Power-On-Reset
The iC-TW2 contains a built-in Power-On-Reset (POR)
circuitry. The POR keeps the iC-TW2 in reset as long
as the applied power supply voltage does not allow
reliable operation. Once the power supply ramps up
above 1.8 V, the POR releases the reset and the iC-
TW2 starts the configuration cycle. 20 ms after the de-
vice goes out of reset, normal operation begins.
STARTUP(1:0) = 00
RELATIVE
A_U
B_V
Z_W
True relative
operation, A/B
phase relation to
Z is unknown
STARTUP(1:0) = 10
STARTUP(1:0) = 11
ABSOLUTE
A_U
B_V
Z_W
A/B has known
phase relation to
Z (same on each
startup)
BURST
A_U
B_V
Z_W
Burst output to
absolute position
within period
Volts V
DD
3.3 or 5.0 V
Figure 11: Startup behaviour
STARTUP(1:0)
Addr. 0x01; bit 4:3
R/W
1.8 V
Code
00
Function
RELATIVE
A/B output signals are kept low during startup. This
resembles true relative operation since there is no
relationship between A/B levels and sensor position
(and therefore Z output) on startup.
0.0 V
Time
iC-TW2 starts A/B
pulse generation.
Power supply and
sensor input signals
should be stable to
avoid A/B toggling.
20 ms
Power- On- Reset releases,
iC-TW2 starts configuration
01
10
Reserved
ABSOLUTE
A/B output signals are phase-related to Z output.
A/B output levels are defined by the absolute
sensor position within a period. The register IPOS
can be used to program the desired A/B to Z phase
relationship.
Figure 10: Power supply ramp-up
11
BURST
The absolute sensor position within the period is
output by an A/B burst.
To avoid A/B output toggling it is important that the
power supply and the input signals are stable as soon
as normal operation begins. In applications with a
slowly rising power supply, it might be necessary to
connect an external RC reset to pin NRST to prolong
the reset. In applications where startup A/B toggling
is acceptable, no precaution must be taken as the iC-
TW2 will properly power up on an indefinitely slow sup-
ply rise time.
Table 29: Startup sequence selection
Reset
A control bit RESET is provided to block any burst
A/B pulses during chip reconfiguration by a microcon-
troller. While RESET is set A/B/Z output generation is
stopped. Access to the interface and register bank is
not affected.
RESET
Addr. 0x01; bit 6
Function
R/W
Code
The iC-TW2 startup behaviour is controlled by pro-
gramming the two control bits STARTUP(1:0) in reg-
ister 0x01. Three possible startup configurations are
allowed, shown in Figure 11. The default behaviour
must be specified by the eeprom.
0
1
normal operation default
initiate reset
Table 30: Restart interpolation engine
ICHAUS [ IC-HAUS GMBH ]
