iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 26/30
shown in Figure 18. A zero-bit is encoded as a short
1W-Interface
The 1W-Interface provides a write-only access port to low followed by a long high. A one-bit is encoded as a
the register bank. It is intended as a minimal con- long low followed by a short high. The modulated sig-
figuration interface to program the internal EEPROM nal is independent of the receiver or transmitter clock
during in-field service or production. An infrared pho- frequency. Since the iC-TW2 uses a free-running oscil-
totransistor can directly connect to the pin to build a lator, it is important to implement a robust, frequency-
cost effective wireless write port. The input bit stream insensitive protocol.
is pulse-width modulated (or duty-cycle modulated) as
1
1
idle
idle
0
0
0
t0low
t1low
t
t
1hi
0hi
Figure 18: Pulse width modulated bit stream
The interface timing is specified in the following Table.
1W- / 2W-Interface is allowed or data corruption
might occur.
Parameter Description
min
max
3. Finally the register content, after a device reset
and configuration, should be verified to ensure a
successfull EEPROM write sequence.
t0low
t0hi
t1low
t1high
Low time bit 0
High time bit 0
Low time bit 1
High time bit 1
40 µs
120 µs
120 µs
40 µs
100 µs
200 µs
200 µs
100 µs
Writing the registers to the EEPROM using EE_WRITE
takes up to 100 msec. During this access to the reg-
ister bank either through the 1W- or 2W-Interface is
prohibited. Any access will corrupt data written to the
EEPROM.
Table 33: 1W-Interface timing
1W-Interface write sequence
Figure 19 describes the write sequence to the regis-
ter bank, which uses the same protocol as the 2W-
Interface. On an idle wire, a write sequence is initiated
by writing a start bit (1) followed by the write command
(00) followed by the address and register data. At the
end of the sequence, a stop-bit (0) is required.
EE_WRITE
Addr. 0x0E; bit 6
W
Code
Function, bit is automatically reset upon completion
of operation
0
1
Normal operation (default)
Store registers into EEPROM
1W-Interface write access to the EEPROM bank is
shown in Figure 20. The 4 bit EEPROM command af-
ter the start bit is decoded in Table 31.
Table 34: EEPROM store command
1
0
0
address(4:0)
data(7:0)
0
idle
idle
Writing the register bank to the EEPROM
To permanently store a configuration in the internal
EEPROM the following procedure should be followed.
Start
Bit
Stop
Bit
Write to Register bank
Regbank
address
8 bit register data
Figure 19: 1W-Interface register bank write se-
quence
1. The 1W- / 2W-Interface is used to fully write the
desired configuration into the register bank.
0
1
c
1
e
b
address(2:0)
data(31:0)
idle
idle
2. A logic one is written to bit EE_WRITE of regis-
ter 0x0E. This will initiate a write sequence which
copies all registers into the internal EEPROM. A
complete write takes 100 ms. During this time,
no access to the register bank through either the
EEPROM
command
Start
Bit
Stop
Bit
EEPROM bank
address
32 bit EEPROM
data
Figure 20: 1W-Interface EEPROM write sequence
ICHAUS [ IC-HAUS GMBH ]
