iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 20/30
FREQ(6:0)
Code
Addr. 0x05; bit 6:0
R/W
Hysteresis is dependent upon chosen accuracy. The
Table below is valid for high accuracy operation.
Function, defaults to eeprom setting
0x00
fcore = fsystem
HYST(1:0)
Addr. 0x06; bit 1:0
R/W
Code
00
Function, defaults to eeprom setting
. . .
no hysteresis
±1.4 °
fsystem
fcore
=
01
1 + FREQ(6 : 0)
10
±2.81 °
0x7F
11
±5.63 °
fsystem
fcore
=
128
Table 25: Master clock divider
An averaging filter can be enabled to remove loop in-
stability noise. It is recommended to enable the fil-
ter in almost all cases. Enabling the filter increases
SIN/COS input to A/B output latency. See Table 22 on
page 19 for details.
Table 23: Maximum input frequency selection
Interpolation setting (register 0x02) in conjunction with
the frequency divider (register 0x05) defines the iC-
TW2’s accuracy mode. Table 21 explains the corre-
lation. Based on the selected accuracy mode other
system parameters are defined as shown in Table 22.
FILTER(1:0)
Addr. 0x06; bit 3:2
Function, defaults to eeprom setting
filter disabled
R/W
Code
00
It is recommended to use the divider at all times when
support for high input frequencies is not required.
01
Average of 8 samples
Average of 16 samples
undefined
10
11
CLKDIV
Addr. 0x0B; bit 1
Function, defaults to eeprom setting
fsystem = fosc
R/W
Code
Table 26: Datapath filter control
0
1
f
osc
fsystem =
2
Table 24: Master clock divider
DEVICE IDENTIFICATION
IDA(3:0)
Addr. 0x00; bit 7:4
Function, Major device identification
R/W
IDB(3:0)
Addr. 0x00; bit 3:0
R/W
Code
Code
Function, Minor device identification
Mask Programmed Value Identifies Major Revision
Mask Programmed Value Identifies Minor Revision
Table 27: Major device revision
Table 28: Minor device revision
ICHAUS [ IC-HAUS GMBH ]
