iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 24/30
SCLK
SDAT
a2
a1
a0
d31
d30
d0
1
1
0
0
0
0
1
3 bit address
32 bit data
SDAT is sampled on
falling edge of SCLK
SDAT is driven externally
SDAT is driven by iC-TW2
extra clocks before
new access
new access
Figure 16: EEPROM read access on 2-wire interface
The 3 bit address a(2:0) selects the EEPROM register to avoid any contention on SDAT while reversing data
to write to (Figure 12). Each EEPROM register is 32 flow direction. Finally d(31:0) is shifted out on SDAT.
bits wide, therefore 32 data bits d(31:0) are sent across EEPROM read access is slow. Please take notice of
the interface. At least 20 ms delay is required after ev- the timings in Table 32.
ery transaction before any new access can start.
At least one extra clock with SDAT low is required after
EEPROM read access is shown in Figure 16. The start every transaction on the 2-wire interface before a new
bit is followed with the 4 bit read command 1100 and access is started. The interface will not work correctly
the 3 bit address a(2:0). An idle clock cycle is used if this clock cycle is omitted.
EEPROM Commands
c 1 e b Description
Purpose
0 1 0 0 Erase followed by write
0 1 0 1 Block erase followed by block write
0 1 1 0 Block write
Normal EEPROM programming
Test only
0 1 1 1 Read. Please refer to Figure 16 for more details
1 1 0 1 Reserved. Do not use this command
1 1 1 0 Erase
Test only
1 1 1 1 Block erase
Special production environment
Table 31: EEPROM Commands
2W-Interface timing
t
t
sclkL
sclkH
The timing of the 2W-Interface is dependent on the
type of access performed. Register bank access and
EEPROM write access can be performed at full speed.
EEPROM read access requires a slow SCLK. Also a
20 ms delay is required after every EEPROM write ac-
cess before a new transaction of any kind is started
(this includes read and write to the register bank).
t
t
sdataH
sdataS
tclk2sdata
tclk2sdata
Figure 17: 2W-Interface timing diagram
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