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IC-TW2 参数 Datasheet PDF下载

IC-TW2图片预览
型号: IC-TW2
PDF下载: 下载PDF文件 查看货源
内容描述: 8 - BIT单/集成了EEPROM COS插值IC [8-BIT SIN/COS INTERPOLATION IC WITH INTEGRATED EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 30 页 / 459 K
品牌: ICHAUS [ IC-HAUS GMBH ]
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iC-TW2 8-BIT SIN/COS INTERPOLATION IC  
WITH INTEGRATED EEPROM  
Rev D3, Page 27/30  
TEST MODES  
EN_MON  
Addr. 0x0B; bit 3  
Function  
R/W  
The iC-TW2 provides various control bits located in dif-  
Code  
ferent registers to enable or disable certain test modes.  
The majority of these is only required for extended chip  
testing capability, others are required for production  
test.  
0
1
Position monitor disabled default  
Monitor enabled  
Table 39: Position monitor control  
GRANULAR  
Addr. 0x05; bit 7  
Function, test mode only  
normal operation  
R/W  
Code  
MONITOR(7:0)  
Addr. 0x0F; bit 7:0  
R/W  
0
1
Code  
Function  
test mode only  
Access to the internal absolute period position. RT  
only!  
Table 35: A/B output edge granularity control  
Table 40: Monitor register  
VC(1:0)  
Code  
Addr. 0x0A; bit 6:5  
R/W  
Function, test mode only  
EE_READ  
Addr. 0x0E; bit 7  
Function  
Normal operation  
W
register must be set to 0 for correct device  
functionality  
Code  
0
1
Read all iC-TW2 registers from the EEPROM. Bit is  
automatically reset upon completion. Not required  
during normal operation since this is done  
automatically on start-up.  
Table 36: Reference voltage fine tuning  
CLKMODE  
Addr. 0x0B; bit 0  
Function, test mode only  
R/W  
Code  
Table 41: EEPROM read command register  
0
1
Select comparator clock default  
Select direct oscillator clock  
Production test control bits  
Production test control bits are reserved bits. Do not  
use the production test control bits during normal op-  
eration. Keep reserved bits ”0”.  
Table 37: Clock source select  
CLKDLY  
Addr. 0x0B; bit 2  
Function  
R/W  
Code  
Reserved  
Reserved  
Reserved  
Code  
Addr. 0xC; bit 7:1  
Addr. 0xD; bit 7:0  
Addr. 0xE; bit 2:0  
R/W  
R/W  
R/W  
0
1
Normal operation  
Add clock delay  
Function  
Table 38: Clock distribution delay line selection  
0
Normal operation  
1 . . .  
Do not use or alter to  
Enabling the position monitor will allow access to the  
internal absolute period position. The position can be  
read through register 0x0F. This is considered a test  
mode and should not be used during normal opera-  
tion.  
Table 42: Test modes