iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C1, Page 30/36
If data from several consecutive registers is to be read ter one byte checks the data returned from the mas-
out (see Figure 12), the autoincrement function en- ter for errors. Once the required number of register
ables an abbreviated transmission protocol to be run values has been sent the slave transmits the address
using iC-JX. Here the master does not send a 0 code of the last register addressed, followed by the control
after the address of the first register value and the NOP byte 0b01011001 with error-free transmission or the in-
byte but the number of registers to be read out mi- verted value 0b10100110 with an error in transmission.
nus one (an entry of 1..15 results in a readout of 2..16 During transmission of the control byte the synchro-
bytes). Here, too, the inverted value is transmitted in nism of the signals at SI and SOx is again checked; if
the second nibble of the byte. The addressed iC-JX these are not synchronous, on recognition of this fact
then transmits the consecutive register values and af- the slave then transmits the inverted control byte.
Figure 12: Reading several values of consecutive register addresses (autoincrement)
Writing to an iC-JX (Figure 13, Figure 14):
Data from consecutive addresses is then sent. iC-JX
returns the master data with a delay of one byte, al-
In the write process one or several registers can be lowing the master to constantly monitor whether an er-
written to during a transmit cycle. To this end the ror has occurred during the addressing sequence or
master first sends the start address and the numeri- data transmission. If an error is detected, the master
cal amount of data to be transmitted minus one. As in can prevent the faulty data being accepted by the slave
the read process this value is transmitted as two nib- registers by ending communication.
bles (non-inverted and inverted) to increase security.
Figure 13: Writing one register value
Figure 14: Writing several register values