iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C1, Page 27/36
5V 5V
24V
24V
24V
C2
C1
100 nF
100 nF
5V
VDD
VCC POE
NSP
VB1
IO1
IO2
Nibble 0
Nibble 1
Nibble 2
Nibble 3
S1
S2
S3
S4
NCS
NWR
NRD
NCS
IO3
IO4
5V
S1
A0
A1
A2
VB2
S2
S3
S5
S6
S7
S8
IO5
IO6
IO7
IO8
R1
S9
A3
A4
SCK
R2
S4
R3
R5
D0
MOSI
VB3
IO9
R4
S10
R7
SOC
R6
S11
R9
MISO
MISO
I010
alternative
alternative
R10
SOB
D3
R8
S12
I011
I012
S13
D4
µC
D5
D6
D7
VB4
IO13
IO14
IO15
IO16
LA1
LA2
REL1
REL2
optional
optional
NINTN
NRES
NINT
AD
CONTROL
REGISTER
iC-JX
CONVERTER
NRES
MQFP52
RSET VREF BLFQ CLK
GNDA GNDD
5V
5V
optional
1.25MHz
RESET
CONTROLLER
2.5V
5V
10 Hz
Figure 7: Example application using a serial interface
Several iC-JXs can be operated on an SPI. If the de- mode; the others remain transparent so that commu-
vices are to be configured as a chain, up to three can nication between the controller and addressed iC-JX
be placed in a row; with buses, four devices can be can take place without delay. It must be noted here
used. To this end iC-JX’s SPI has both a clock input that even in transparent mode each iC-JX has a cer-
(SCK) and chip select input (NCS) and a data input tain transmit time which has an effect on the maximum
(SI) and data output for chain operation (SOC, Serial data frequency of the overall system. The advantage
Out Chain) and bus operation (SOB, Serial Out Bus).
of this configuration lies in the fact that it is possible to
The configuration is set using pin A2. If this is at 0, the read out the values of an address in all devices very
devices are in chain operation; if this is at ’1’, the chips quickly.
switch to bus configuration.
In bus configuration (see Figure 8, bottom ) all SI inputs
In chain configuration (see Figure 8, top) output SOC and SOB outputs are switched in parallel; the SOC out-
of a device is connected up to the SI data input of the puts are not used. Addressing the devices ensures
following chip; output SOB is not used. During the ad- that only one of the chips outputs data to SOB; the
dressing sequence (1 byte of communication) all iC- outputs of the inactive iCs are switched to tristate. This
JXs are switched through transparently so that all de- type of configuration differs from chain configuration in
vices receive the transmitted address simultaneously. that it permits higher clock rates and also allows up to
Only the addressed chip then goes into data transfer four iC-JXs to be connected up to an SPI bus.
ICHAUS [ IC-HAUS GMBH ]
