iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C1, Page 34/36
in the overcurrent message register (addresses 0x06 can be deleted by setting EOI to 1 in control word 4
and 0x07).
(address 0x1A). Should the supply voltage then again
rise to VCCon or VDDon, iC-JX assumes a reset state.
At addresses 0x08 and 0x09 the actual, unfiltered
overcurrent status of each I/O stage can be read; a Undervoltage detection: VB1...4
global scan of all I/O stages is also possible via bit SCS In order to guarantee the fail-safe operation of con-
in the interrupt status register. This shows whether nected loads voltage VB is also monitored. If the volt-
any of the I/O stages have overcurrent at the time of age drops below threshold VBoff the I/O outputs are
the readout. This short-circuit messaging allows per- disabled. Neither a device reset nor an interrupt mes-
manent monitoring of the output transistors and clear sage to the microcontroller are then triggered. Once
allocation of error message to affected I/O stage. Fil- voltage VB again rises above VBon the I/O outputs are
tering of the overcurrent message can be shutdown re-enabled. The microcontroller can read out the sta-
using a bypass; this bypass can be activated for all I/O tus of voltage VB at bit DID1 in the device ID register
stages together using BYPSCF in control word 4 (ad- (address 0x0C). In the event of error (VB < VBoff) this
dress 0x1A).
bit is set to 1.
Temperature monitoring
Pin monitoring GNDD and GNDA
iC-JX has a two-stage temperature monitor circuit.
iC-JX includes a pin watchdog circuit which monitors
the connection between the two ground pins GNDA
and GNDD. The microcontroller can detect a possible
error, such as a disconnected iC lead, for example, by
reading bit IBA in the device ID register. In the event
of error this is set to 1. If such a case of an error is
present, then the potential of the missing ground pin is
raised, which can lead to the shift of the trigger levels.
Stage 1: A warning interrupt is generated if the first
temperature threshold (Toff1 at ca. 132 °C) is ex-
ceeded. Suitable measures to decrease the power
dissipation of the driver can be implemented using
the microcontroller.
Stage 2: If the second temperature threshold is ex-
ceeded (Toff2 at ca. 152 °C), a second interrupt
is generated. At the same time the output tran-
sistors and the I/O stage current sources are shut-
down and the output register and flash pulse en-
able deleted. Once the temperature has returned
to below the level of Toff1 the current sources are
reactivated. The output register and flash pulse en-
able have to be respecified to reactivate the output
stages
Burst detection at VDD
As in principle bursts at VDD can influence the con-
tents of registers iC-JX monitors spikes in the supply.
If any hazard is detected interupt outputs are set to 0.
Stored interrupt message ISD (interrupt status register
B, address 0x05) can be deleted by setting EOI to 1 in
control word 4 (address 0x1A).
Device identification
An identification code has been introduced to enable
identification of iC-JX. Bit pattern 0b10101 can be read
out at address 0x0D.
The interrupt status register (address 0x04) provides
information as to the temperature interrupt stage but
also on the current status of the temperature moni-
tor. ET2 and ET1 statically indicate when Toff2 and
Toff1 are exceeded, whereby stored interrupt mes-
sages IET2 and IET1 and the display at NINT via EOI =
1 can be deleted (control word 4, address 0x1A).
Reset
A reset (NRES = 0) sets the register entries to the reset
values given in the tables.
Operation without the BLFQ signal
Should no clock signal be available at pin BLFQ iC-JX
can generate an internal flash pulse from the exter-
Undervoltage detection: VCC and VDD
When the supply voltage at VCC or VDD is switched nal clock signal at pin CLK or from clock signal ICLK
on the output transistors are only released by the un- which is generated internally. For the flash frequency
dervoltage detector after power-on enables VCCon or to be derived from the system clock pulse bit SEBLQ in
VDDon have been reached. Should the supply volt- control word 3B (address 0x19) must be set to 1. The
age drop to VCCoff or VDDoff during operation the flash period is then calculated by dividing by 2 19
I/O stages are disabled, i.e. the output transistors are
.
turned off and the device reset. At the same time in- Operation without the CLK signal
terrupt outputs are set. USD and USA in interrupt sta- iC-JX can also be operated without a clock pulse at pin
tus register B (address 0x05) statically indicate under- CLK. Using control word 3B (address 0x1A) the device
voltage at VCC and VDD. Stored interrupt messages can be set to an internally generated clock frequency;
IUSD and IUSA and the display at NINT or SO(D1) In this instance all filter functions remain fully available.
ICHAUS [ IC-HAUS GMBH ]
