iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C1, Page 33/36
For the mode "Overall Voltage Measurement at IO" the from CLK or from the internally generated ICLK (via
voltage at the selected I/O stage is downscaled first by SEBLQ in control word 3B, address 0x1A). Different
a factor of 1/15 using a resistive voltage divider to per- flash frequencies can be set for all four nibbles.
mit measurement of the full voltage range from rail to
rail. The user must be aware of a input current drawn
by the voltage divider of approimately V(IO)/200kΩ.
The selection of the I/O stage is done via control word
5 (Adr. 0x1B).
Interrupts
Interrupt readings at NINT can be triggered by a
change of (filtered) input signal, by an overcurrent
message signaled at an I/O pin (due to a short cir-
cuit, for example), by undervoltage at VCC or VDD, by
bursts at VDD, by the end of A/D conversion or by ex-
ceeding maximum temperature thresholds (2 stages).
Interrupt outputs for each individual I/O stage can be
caused by a change of input, or, with stages in output
mode, by a short circuit. The relevant interrupt enables
determine which messages are stored and which are
displayed. The display of interrupt messages caused
by excessive temperature, A/D conversion, undervolt-
age or bursts is not maskable; this particular function
is permanently enabled.
ADC Measurements: VBy and VBG Measurements
(Adr. 0x1C)
The internal reference voltage VBG and the external
supply voltages VB1 to VB4 can also be measured.
For VB1 to VB4, the voltage is downscaled first by a
factor of 1/15. Selection is done via SELES (3:0) in
control word 5 (Adr. 0x1B) as described in the follow-
ing table.
SELES(3:0) VB - Messung
When an event occurs which is enabled to produce an
interrupt message pin NINT is set to 0 when a parallel
interface is used. If the device is being operated with
a serial interface outputs D1/SOC or D2/SOB are set
to 0 when an interrupt occurs if no communication is
made via the interface itself and pin A4 ist set to ’1’ .
By reading out the interrupt status register (addresses
0x04 and 0x05) the nature of the message can be de-
termined and the I/O stage causing the interrupt lo-
cated. Thus with a change-of-input message the prob-
lematic I/O stage is shown in the corresponding regis-
ter (addresses 0x02 and 0x03); with an overcurrent in-
terrupt the overcurrent status register (addresses 0x06
and 0x07) pinpoints the I/O stage with a short circuit.
Interrupts are deleted by simply setting EOI in control
word 4 (address 0x1A). This bit then automatically re-
sets to 0. If during operation the I/O mode is switched,
i.e. from input to output mode, all interrupt messages
are deleted via EOI.
To avoid interrupt messages caused by other sources
in the time between the readout of a status register and
the deletion of the current interrupt being overlooked
successive interrupts are stored in a pipeline. If suc-
cessive interrupts occur outputs NINT resp. D1/SOC
or D2/SOB remain at 0 after the present interrupt has
been deleted using EOI. The new interrupt source is
displayed in the interrupt status register and in the spe-
cific status registers.
0x0 .. 0x3
0x4 .. 0x7
0x8 .. 0xB
0xC .. 0xF
VB1
VB2
VB3
VB4
ADC Measurements: Temperature Measurement
(Adr. 0x1C)
In this feature the internal chip temperature can be de-
termined.
ADC Measurements: External Vref (Adr. 0x1C)
To improve accuracy of the A/D conversion, an exter-
nal reference voltage at pin VREF can be used by set-
ting the bit SVREF to ’0b1’. The value of the external
voltage reference should be about 2.5V ±0.2%.
ADC Measurements: Output
A 10 bit digital value as a result of A/D convertion is
available for output currents and output voltages at a
selected I/O stage, for chip temperature and supply
voltages Vby and the internal bandgap voltage VBG.
Except for the current measurement, the internal volt-
age V(VREFAD) (for Bit SVREF = ’0’) or an external
voltage at pin Vref (for Bit SVREF = ’1’) are used as
reference. The end of A/D conversion is signalled by a
low signal ’0’ at NINT resp. D1/SOC or D2/SOB.
Output register (Adr. 0x0C und 0x0D):
Switches the various output stages on and off (for
POE = 1).
Overcurrent messages
If an overload occurs at one of the outputs the current
in IOx is limited. In this instance an interrupt message
is triggered, providing relevant interrupt enables have
been set for overcurrent messages (addresses 0x12
Flash pulse enable (addresses 0x0E und 0x0F):
Enables flash mode
This function enables each of the various output stages and 0x13) and the filter time set with control word 4
to be set to flash mode, providing the value of the cor- (address 0x1A) has elapsed. ISCI is then set in the
responding output register is 1. The flash frequency is interrupt status register (address 0x04) and the rele-
derived from BLFQ or, alternatively, can be generated vant bit for the I/O stage causing the problem is set
ICHAUS [ IC-HAUS GMBH ]
