iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C1, Page 29/36
Note must be taken here of the fact that in chain config- casting (see page ??); the other addresses are used
uration the device ID 0b00 is not permissible. If it is set, to select an individual chip. In chain configuration up
the device acts as if it did not exist (and is permanently to three devices can thus be driven on an SPI master.
transparent). This makes it possible to test the deac- In bus configuration address 0b00 has no special func-
tivation of a chip without blocking the interface. Used tion, making it possible to address four iC-JXs with one
in chain configuration, the address 0b00 addresses all NCS line.
iC-JXs simultaneously in a process known as broad-
Figure 10: Addressing sequence
Reading from an iC-JX (Figure 11):
while the master sends an NOP (no operating) byte.
The slave then sends the required data. The master
In both types of configuration one or more values can sends the number of bytes to be read out minus one (in
be read during a transmit cycle. The first byte sent this case the value 0). To increase security the number
by the controller (master) is the address the data is to byte is split into two nibbles which are encoded with the
be read out from. The activated iC-JX (slave) sends original and inverted value (0 → 0b00001111).
the address back in the next byte by way of verification
Figure 11: Reading a single register value
If verification in whatever form is dispensed with, the For its part the slave checks that the returned data is
master can end the read cycle at this point. The mas- correct; if this is so, it then also transmits the control
ter otherwise sends the received data back to the slave byte 0b01011001. In the event of error an inverted
which then returns the address of the read register (in value of 0b10100110 is sent. During the transmission
this instance the start address) by way of verification. of this control byte the setup also checks whether the
If this does not match the one originally sent by the signals at SI and SOx are synchronous. If this is not
master, the master can then abort communication and the case (due to a spike occurring at SCK, for exam-
repeat if necessary. If the address is correct, in the ple), the slave transmits the inverted control byte as
next stage of the procedure the master transmits the soon as it has detected the error.
control byte optimized for maximum error recognition The master recognizes a correct transmission by the
(0b01011001).
fact that the control byte has reached it without error.
ICHAUS [ IC-HAUS GMBH ]
