iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C1, Page 28/36
iC-JX
iC-JX
iC-JX
SOC
SI
NCS SCLK SOB
SOC
SOC
SI
SI
NCS SCLK SOB
NCS SCLK SOB
MOSI
NCS
SCK
MISO
SOC
SOC
SOC
SOC
iC-JX
iC-JX
iC-JX
iC-JX
SI
SI
SI
SI
NCS SCLK SOB
NCS SCLK SOB
NCS SCLK SOB
NCS SCLK SOB
MOSI
NCS
SCK
MISO
Figure 8: Possible SPI configurations
If no communication takes place on the SPI the chips Using pin A4 settings can be made as to whether inter-
can send interrupts to the controller by switching the rupts are signaled to the master via the SOB or SOC
master MISO line to 0. To this end all iC-JXs in chain (0 = no interrupt message; 1 = interrupt message). The
configuration are switched through transparently (see message must be deactivated in bus configuration if
Figure 9). In bus configuration the relevant chip drives further devices are present on the SPI bus as other-
a 0 at its SOB output towards the pull-up resistors at wise data can collide on the bus which is not desirable
the outputs of the other devices.
here.
3..5.5V
0V
VDD
GND
JX-Logic
NINT
JX-Logic
JX-Logic
NINT
Address
Address
Address
SEL
JX1
JX2
JX3
SEL
SEL
Comparator
Comparator
Comparator
NINT
Evaluation
Evaluation
Evaluation
NERR
NERR
NERR
Shift register
Shift register
Shift register
D1/
SOC
D1/
SOC
D1/
SOC
D0/SI
D0/SI
D0/SI
&
&
&
A3/SCK NCS
A3/SCK NCS
A3/SCK NCS
MISO
SCK
NCS
MOSI
Figure 9: Addressing and interrupt messaging scheme in chain configuration
The first byte of communication (see Figure 10) con- ister address (RA4:0) and a read-not-write (RNW) bit.
sists of the 2-bit chip address (BA1:0), the 5-bit reg- The device ID is set for each chip using pins A(1:0).
ICHAUS [ IC-HAUS GMBH ]
