IBMN325164CT3
IBMN325804CT3
IBMN325404CT3
Preliminary
256Mb Synchronous DRAM - Die Revision B
Read Cycle
-75H
-75D
-75A
-260
-360
-10
Symbol
Parameter
Units Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
—
2.7
0
—
—
—
2.7
0
—
—
—
5.4
—
—
—
2.7
0
—
—
—
5.4
—
—
2.5
3
—
—
—
6
2.5
3
—
—
—
6
3
3
0
3
3
2
—
—
—
7
ns
ns
ns
ns
ns
CK
1
t
Data Out Hold Time
OH
2, 4
t
Data Out to Low Impedance Time
Data Out to High Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
—
0
0
LZ
t
t
3
5.4
5.4
—
3
3
3
3
3
3
HZ3
HZ2
3
—
2
—
2
3
6
3
8
8
t
2
2
—
2
—
—
DQZ
1. AC Output Load Circuit A.
2. AC Output Load Circuit B.
3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
4. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A).
Refresh Cycle
-75H
-75D
-75A
-260
-360
-10
Symbol
Parameter
Units Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
t
Refresh Period
—
10
64
—
—
10
64
—
—
10
64
—
—
10
70
64
—
—
10
70
64
—
—
10
84
64
—
ms
ns
ns
1
2
REF
t
Self Refresh Exit Time
SREX
t
Bank Cycle Time (Auto Refresh)
67.5
67.5
67.5
RFC
1. 8192 auto refresh cycles.
2. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows; the num-
ber of clock cycles = specified value of timing/clock period (count fractions as a whole number).
Write Cycle
-75H
-75D
-75A
-260
-360
-10
Symbol
Parameter
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
t
Data In Set-up Time
Data In Hold Time
1.5
0.8
15
—
—
—
1.5
0.8
15
—
—
—
1.5
0.8
15
—
—
—
2
1
—
—
—
2
1
—
—
—
3
1
—
—
—
ns
ns
ns
DS
t
DH
t
Data input to Precharge
20
20
20
DPL
Data In to Active Delay
CAS Latency = 3
t
5
—
5
—
5
—
5
—
5
—
5
—
CK
DAL3
DAL2
Data In to Active Delay
CAS Latency = 2
t
5
0
—
—
—
0
—
—
—
0
—
—
5
0
—
—
5
0
—
—
3
0
—
—
CK
CK
t
DQM Write Mask Latency
DQW
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K0608.F39375A
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