(Burst length = 4, CAS latency = 2)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CK
tCK2
tCKH
tCKL
tCS
CKE
CS
tCES
tCEH
tCH
RAS
CAS
WE
* BA1
tAH
RAz
RAz
RBy
A10
RAx
RBx
RBx
RAy
tAS
A0-A9,
A11,A12
RBy
RAx
CAx
CBx
RAy
CAy
DQM
tRCD
tDAL‡
tDPL‡
tDS
tRC
tDH
tRP
tRRD
Hi-Z
Ax0
Ax1
Ax2
Ax3
DQ
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
*BA0 = ”L”
Bank2,3 = Idle
Activate
Write with
Activate
Write with
Activate
Write
Command
Bank 0
depend on clock cycle time and
Activate
Command
Bank 1
Activate
Command
Bank 0
Precharge
Command
Bank 0
Command Auto Precharge Command Auto Precharge
Command
Bank 0
Bank 0
Command
Bank 0
Bank 1
Command
Bank 1
‡
t
and t
DPL
DAL
speed sort. See the Clock Frequency and
Latency Table.
IBM [ IBM ]
