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IBMN325404CT3B-75H 参数 Datasheet PDF下载

IBMN325404CT3B-75H图片预览
型号: IBMN325404CT3B-75H
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 64MX4, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 66 页 / 1699 K
品牌: IBM [ IBM ]
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IBMN325164CT3  
IBMN325404CT3  
IBMN325804CT3  
256Mb Synchronous DRAM - Die Revision B  
Preliminary  
Operating, Standby, and Refresh Currents (TA = 0 to +70°C, VDD = 3.3V ±0.3V)  
Speed  
Parameter  
Symbol  
Test Condition  
Units Notes  
-75H -75D -75A -260  
-360  
115  
-10  
90  
1 bank operation  
= t (min), t = min  
t
RC  
RC  
CK  
Operating Current  
I
130  
130  
120  
115  
mA  
1, 2, 3  
CC1  
Active-Precharge command  
cycling without burst operation  
CKE V (max), t = min,  
IL  
CK  
I
2
2
2
2
2
2
2
2
2
2
2
2
mA  
mA  
1
1
CC2P  
CS = V (min)  
IH  
Precharge Standby Current  
in Power Down Mode  
CKE V (max), t = Infinity,  
IL  
CK  
I
CC2PS  
CS = V (min)  
IH  
CKE V (min), t = min,  
IH  
CK  
I
30  
8
30  
8
30  
8
20  
8
20  
8
20  
8
mA  
mA  
mA  
mA  
1, 5  
1, 7  
1, 5  
1, 6  
CC2N  
Precharge Standby Current  
in Non-Power Down Mode  
CS = V (min)  
IH  
I
CKE V (min), t = Infinity,  
IH CK  
CC2NS  
CKE V (min), t = min,  
IH  
CK  
I
60  
6
60  
6
60  
6
45  
6
45  
6
45  
6
CC3N  
No Operating Current  
(Active state: 4 bank)  
CS = V (min)  
IH  
I
CKE V (max), t = min,  
CC3P  
IL  
CK  
t
= min,  
CK  
Operating Current (Burst  
Mode)  
Read/ Write command cycling,  
Multiple banks active, gapless  
data, BL = 4  
I
120  
120  
120  
90  
90  
90  
mA  
1, 3, 4  
CC4  
t
= min, t = t (min)  
RC RC  
CK  
Auto (CBR) Refresh Current  
Self Refresh Current  
I
I
175  
3
175  
3
175  
3
155  
3
155  
3
140  
3
mA  
mA  
1
1
CC5  
CBR command cycling  
CKE 0.2V  
CC6  
1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed on the  
other deck.  
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input  
signals are changed up to three times during tRC(min).  
3. The specified values are obtained with the output open.  
4. Input signals are changed once during tCK(min).  
5. Input signals are changed once during three clock cycles.  
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).  
7. Input signals are stable.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
06K0608.F39375A  
10/00  
Page 36 of 66  
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