IBMN325164CT3
IBMN325404CT3
IBMN325804CT3
256Mb Synchronous DRAM - Die Revision B
Preliminary
Clock Frequency and Latency
Symbol
Parameter
Clock Frequency
-75H
133
7.5
2
-75D
133
7.5
3
-75A
133
7.5
3
-260
100
-360
100
-10
Units
f
100
10
2
66
15
2
100
10
3
71
MHz
ns
CK
t
Clock Cycle Time
10
3
2
2
7
7
5
2
5
2
1
0
0
2
1
10
3
2
2
7
7
5
2
5
2
1
0
0
2
1
14
2
1
2
5
5
4
2
3
2
1
0
0
2
1
CK
t
CAS Latency
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
AA
RP
t
Precharge Time
2
2
3
2
2
3
t
RAS to CAS Delay
2
2
3
2
2
3
RCD
t
Bank Cycle Time
8
8
9
7
6
9
RC
t
Bank Cycle Time (Auto Refresh)
Minimum Bank Active Time
Data In to Precharge
Data In to Active/Refresh
Bank to Bank Delay Time
CAS to CAS Delay Time
Write Latency
9
9
9
7
6
9
RFC
t
6
6
6
5
4
6
RAS
t
2
2
2
2
2
2
DPL
DAL
t
5
5
5
5
5
5
t
2
2
2
2
2
2
RRD
CCD
t
1
1
1
1
1
1
t
0
0
0
0
0
0
WL
t
DQM Write Mask Latency
DQM Data Disable Latency
Clock Suspend Latency
0
0
0
0
0
0
DQW
t
2
2
2
2
2
2
DQZ
t
1
1
1
1
1
1
CSL
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Use is further subject to the provisions at the end of this document.
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