IBMN325164CT3
IBMN325804CT3
IBMN325404CT3
Preliminary
256Mb Synchronous DRAM - Die Revision B
AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ± 0.3V)
1. An initial pause of 200µs, with DQM and CKE held high, is required after power-up. A Precharge All
Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before or after
the Mode Register Set operation.
2. The Transition time is measured between V and V (or between V and V )
IH
IL
IL
IH
3. In addition to meeting the transition rate specification, the clock and CKE must transit between V and
IH
V (or between V and V ) in a monotonic manner.
IL
IL
IH
4. Load Circuit A: AC timing tests have V = 0.4 V and V = 2.4 V with the timing referenced to the 1.40V
IL
IH
crossover point
5. Load Circuit A: AC measurements assume t = 1.0ns.
T
6. Load Circuit B: AC timing tests have V = 0.8 V and V = 2.0 V with the timing referenced to the 1.40V
IL
IH
crossover point
7. Load Circuit B: AC measurements assume t = 1.2ns.
T
.
AC Characteristics Diagrams
tT
Vtt = 1.4V
VIH
50Ω
Output
1.4V
VIL
tCKL
tCKH
Clock
Input
Zo = 50Ω
50pF
tSETUP
AC Output Load Circuit (A)
tHOLD
1.4V
Output
Zo = 50Ω
tOH
50pF
tAC
tLZ
AC Output Load Circuit (B)
1.4V
Output
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Use is further subject to the provisions at the end of this document.
06K0608.F39375A
10/00
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