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IBMN312404CT3B-75H 参数 Datasheet PDF下载

IBMN312404CT3B-75H图片预览
型号: IBMN312404CT3B-75H
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 66 页 / 2855 K
品牌: IBM [ IBM ]
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IBMN312164CT3  
IBMN312804CT3  
IBMN312404CT3  
Preliminary  
128Mb Synchronous DRAM - Die Revision B  
Precharge Termination  
The Precharge Command may be used to terminate either a burst read or burst write operation. When the  
Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read  
operations, valid data will continue to appear on the data bus as a function of CAS Latency.  
Burst Read Interrupted by Precharge  
(Burst Length = 8, CAS Latency = 2, 3)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CK  
READ Ax  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Precharge A  
DOUT Ax  
COMMAND  
0
t
RP  
*
CAS latency = 2  
DOUT Ax  
DOUT Ax  
DOUT Ax  
3
0
1
2
tCK2, DQs  
t
RP  
*
DOUT Ax  
3
CAS latency = 3  
DOUT Ax  
DOUT Ax  
DOUT Ax  
0
1
2
tCK3, DQs  
Bank A can be reactivated at completion of tRP  
.
tRP is a function of clock cycle time and speed sort.  
*
See the Clock Frequency and Latency table.  
©IBM Corporation. All rights reserved.  
06K7582.H03335A  
01/01  
Use is further subject to the provisions at the end of this document.  
Page 23 of 66  
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