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IBMN312404CT3B-75H 参数 Datasheet PDF下载

IBMN312404CT3B-75H图片预览
型号: IBMN312404CT3B-75H
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 66 页 / 2855 K
品牌: IBM [ IBM ]
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IBMN312164CT3  
IBMN312404CT3  
IBMN312804CT3  
128Mb Synchronous DRAM - Die Revision B  
Preliminary  
Power Down Mode  
In order to reduce standby power consumption, two power down modes are available: Precharge and Active  
Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary  
precharge delay (t ) must occur before the SDRAM can enter the power down mode. If a bank is activated  
RP  
but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a Power  
Down Mode Command when the device is performing a Read or Write operation causes the device to enter  
Clock Suspend mode. See the following Clock Suspend section.) Once the Power Down mode is initiated by  
holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does not per-  
form any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh  
period (t  
) of the device.  
REF  
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or  
Device Deselect Command) is required on the next rising clock edge.  
Power Down Mode Exit Timing  
Tm  
Tm+1  
Tm+2  
Tm+3  
Tm+4  
Tm+5  
Tm+6  
Tm+7  
Tm+ 8  
CK  
t
CK  
CKE  
t
CES(min)  
NOP  
COMMAND  
NOP  
NOP  
NOP  
NOP  
NOP  
COMMAND  
: “H” or “L”  
©IBM Corporation. All rights reserved.  
06K7582.H03335A  
01/01  
Use is further subject to the provisions at the end of this document.  
Page 26 of 66  
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