IBMN312164CT3
IBMN312804CT3
IBMN312404CT3
Preliminary
128Mb Synchronous DRAM - Die Revision B
Burst Write with Auto-Precharge Interrupted by Read
(Burst Length = 4, CAS Latency = 3)
T6 T7 T8
T0
T1
T2
T3
T4
T5
CK
WRITE A
NOP
NOP
READ B
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
t
‡
DAL
*
CAS latency = 3
tCK3, DQs
DIN A
0
DIN A
DIN A
2
DOUT B
DOUT B
DOUT B
1
0
1
2
Bank A can be reactivated at completion of t
‡ tDAL is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
.
*
DAL
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-
mand is triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Pre-
charge Command can be used to precharge each bank separately or all banks simultaneously. Three
address bits, A10, BS0, and BS1, are used to define which bank(s) is to be precharged when the command is
issued.
Bank Selection for Precharge by Address Bits
A10
LOW
HIGH
Bank Select
BS0, BS1
Precharged Bank(s)
Single bank defined by BS0, BS1
All Banks
DON’T CARE
For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For
write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge Command
can be issued. This delay is known as t
, Data-in to Precharge delay.
DPL
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write
access can be executed. The delay between the Precharge Command and the Activate Command must be
greater than or equal to the Precharge time (t ).
RP
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
Page 21 of 66
IBM [ IBM ]
