IBMN312164CT3
IBMN312404CT3
IBMN312804CT3
128Mb Synchronous DRAM - Die Revision B
Preliminary
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank
undergoing auto-precharge cannot be reactivated until t
, Data-in to Active delay, is satisfied.
DAL
Burst Write with Auto-Precharge
(Burst Length = 2, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
t
‡
DAL
CAS latency = 2
*
tCK2, DQs
DIN A
DIN A
DIN A
0
1
1
t
‡
DAL
*
CAS latency = 3
tCK3, DQs
DIN A
0
Bank can be reactivated at completion of tDAL
‡ tDAL is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
.
*
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command
to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The inter-
rupting command will terminate the write. The bank undergoing auto-precharge can not be reactivated until
t
is satisfied.
DAL
Burst Write with Auto-Precharge Interrupted by Write
(Burst Length = 4, CAS Latency = 3)
T6 T7 T8
T0
T1
T2
T3
T4
T5
CK
WRITE A
NOP
NOP
WRITE B
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
t
‡
DAL
*
CAS latency = 3
t
CK3, DQs
DIN A
DIN A
DIN B
DIN B
DIN B
DIN B
3
0
1
0
1
2
Bank can be reactivated at completion of tDAL
.
*
‡ tDAL is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
Page 20 of 66
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