IBMN312164CT3
IBMN312404CT3
IBMN312804CT3
128Mb Synchronous DRAM - Die Revision B
Preliminary
Burst Read Followed by the Precharge Command
(Burst Length = 4, CAS Latency = 3)
T6 T7 T8
T0
T1
T2
T3
T4
T5
CK
READ Ax
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
COMMAND
0
‡
*
t
RP
CAS latency = 3
DOUT Ax
DOUT Ax
DOUT Ax
2
DOUT Ax
3
0
1
tCK2, DQs
Bank A can be reactivated at completion of tRP
tRP is a function of clock cycle and speed sort.
.
*
‡
Burst Write Followed by the Precharge Command
(Burst Length = 2, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
Activate
Bank Ax
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
WRITE Ax
COMMAND
0
t
‡
t
‡
RP
DPL
*
CAS latency = 2
t
CK2, DQs
DIN Ax
DIN Ax
0
1
Bank can be reactivated at completion of tRP
‡ tDPL and tRP are functions of clock cycle and speed sort.
See the Clock Frequency and Latency table.
.
*
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
Page 22 of 66
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