IBMN312164CT3
IBMN312404CT3
IBMN312804CT3
128Mb Synchronous DRAM - Die Revision B
Preliminary
Burst write operations will be terminated by the Precharge command. The last write data that will be properly
stored in the device is that write data that is presented to the device a number of clock cycles prior to the Pre-
charge command equal to the Data-in to Precharge delay, t
.
DPL
Precharge Termination of a Burst Write
(Burst Length = 8, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
NOP
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
WRITE Ax
COMMAND
DQM
0
t
‡
‡
DPL
CAS latency = 2
tCK2, DQs
DIN Ax
DIN Ax
DIN Ax
DIN Ax
DIN Ax
DIN Ax
0
1
1
2
2
t
DPL
CAS latency = 3
tCK3, DQs
0
‡ t
is an asynchronous timing and may be completed in one or two clock cycles
DPL
depending on clock cycle time.
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
Page 24 of 66
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