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IBMN312404CT3B-75H 参数 Datasheet PDF下载

IBMN312404CT3B-75H图片预览
型号: IBMN312404CT3B-75H
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 66 页 / 2855 K
品牌: IBM [ IBM ]
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IBMN312164CT3  
IBMN312804CT3  
IBMN312404CT3  
Preliminary  
128Mb Synchronous DRAM - Die Revision B  
Data Mask  
The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When  
the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately  
(zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and  
become high impedance after a two-clock delay, independent of CAS latency.  
Data Mask Activated during a Read Cycle  
(Burst Length = 4, CAS Latency = 2)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CK  
DQM  
NOP  
READ A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
COMMAND  
DOUT A  
DQs  
DOUT A  
1
0
A two-clock delay before  
the DQs become Hi-Z  
: “H” or “L”  
No Operation Command  
The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The pur-  
pose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands  
between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held  
high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is  
still executing, such as a burst read or write cycle.  
Deselect Command  
The Deselect Command performs the same function as a No Operation Command. Deselect Command  
occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares.  
©IBM Corporation. All rights reserved.  
06K7582.H03335A  
01/01  
Use is further subject to the provisions at the end of this document.  
Page 27 of 66  
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