IBMN312164CT3
IBMN312404CT3
IBMN312804CT3
128Mb Synchronous DRAM - Die Revision B
Preliminary
Non-Minimum Write to Read Interval
(Burst Length = 4, CAS latency = 2, 3)
T5 T6 T7 T8
T0
T1
T2
T3
T4
CK
NOP
READ B
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DIN A
DIN A
DIN A
0
DOUT B
0
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
1
1
1
2
3
tCK2, DQs
CAS latency = 3
DIN A
0
DOUT B
3
0
1
2
tCK3, DQs
: “H” or “L”
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
Page 16 of 66
IBM [ IBM ]
