IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
5.1.5 Reset Register
Address
x‘05’
Access Type
Reset Value
Read/Write
‘1110 0010 0000 0000 0000 0000 0000 0uuu’, where ‘u’ = undefined
Reserved
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Bit(s)
Field Name
Flush Control
Flush
Description
When set to ‘1’, keeps the device control section in a reset state. For slave devices, this bit must be
set to ‘1’.
0
1
When set to ‘1’, keeps the functions common to the master and slave devices in a reset state.
1
Disables event- and error-generated interrupts to the local processor. The device interrupt
signal (active low) is tristated and pulled up with an external resistor. The Status Register
(page 120) bits are asserted when the corresponding events or errors occur.
2
3
4
Global Interrupt Mask
Output Driver Enable
0
Enables event- and error-generated interrupts to the local processor.
1
0
Enables all device drivers until another configuration disables them.
Disables (tristates) all device drivers except for the SHISerialDataOut driver.
When set to ‘1’, enables the built-in self-test (BIST) controller to start executing the internal logic
BIST as soon as the flush bit is deactivated. This bit can be asserted only while the flush bit is
active. Logic BIST completion is reported via the logic BIST done bit (bit 29). See Section 6.4 Logic
BIST Execution Sequence on page 160 for more information.
Logic BIST
Requested
When set to ‘1’, enables the BIST controller to start executing the memory BIST as soon as the
flush bit is deactivated. This bit can be asserted only while the flush bit is active. Memory BIST com-
pletion and results are reported via the memory BIST done and memory BIST fail bits (bits 30 and
31). See Section 6.5 Memory BIST Execution Sequence on page 161 for more information.
Memory BIST
Requested
5
6
Unilink Macro Flush
Reserved
When set to ‘1’, keeps all Unilink macros in a reset state.
7:28
Reserved.
Logic BIST Done
(read only)
Set to ‘1’ when the BIST controller completes internal processing after a logic BIST request
command.
29
30
31
Memory BIST Done
(read only)
Set to ‘1’ when the BIST controller completes internal processing after a memory BIST request
command.
Memory BIST Fail
(read only)
Set to ‘1’ when, after completion of the memory BIST process, at least one memory BIST check
failed on at least one RAM. This bit is valid only when the memory BIST done bit is asserted.
prsq-64g.01.fm
December 20, 2001
Register Descriptions
Page 69 of 199
IBM [ IBM ]
