IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
Table 5-1. Register Map (Page 3 of 4)
Register Name
Address
x‘31’
Access
Page
108
UL RxSpex Bus Reset BIST Error Register
UL RxSpex BIST Wrap Register
Read/Write
Read/Write
x‘32’
109
Functional Registers: x‘33’ to x‘50’
Configuration 0 Register
x‘33’
x‘34’
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Clear
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
Read/Write
Read/Write
Read/Clear
Read/Clear
Read/Clear
Read/Clear
Read/Clear
Read Only
110
112
114
116
118
120
122
124
124
125
125
126
127
128
129
131
131
132
132
133
Configuration 1 Register
Threshold Access Register
x‘35’
Credit Table Access Register
x‘36’
Best-Effort Resources Access Register
Status Register
x‘37’
x‘38’
Interrupt Mask Register
x‘39’
Output Queue Enable Register
x‘3A’
Input Controller Enable Register
x‘3B’
Bitmap Filter Register
x‘3C’
Color Detection Disable Register
x‘3D’
Expected Color Received Register
x‘3E’
Color Command Register
x‘3F’
Bitmap Mapping Register
x‘40’
Output Queue Status Registers
x‘41’ to x‘48’
x‘49’
Best-Effort Discard Alarm Register
Send Grant Violation Register
x‘4A’
Header Parity Error Register
x‘4B’
Flow Control Violation Register
x‘4C’
Side Communication Channel Input Reporting Registers
Control Packet and Service Packet Transmission Registers: x‘51’ to x‘57’
Egress Control Packet and Service Packet Payload Registers
Egress Control Packet and Service Packet Destination Register
Control Packet and Service Packet Reception Registers: x‘58’ to x‘63’
Ingress Control Packet or Command Service Packet Received Registers
Ingress Control Packet and Service Packet Source Register
Ingress Control Packet and Service Packet Payload Registers
Ingress Event Service Packet Received Registers
Ingress Event Service Packet Mask Registers
x‘4D’ to x‘50’
x‘51’ to x‘56’
x‘57’
Read/Write
Read/Write
134
135
x‘58’ to x‘5B’
x‘5C’
Read Only
Read/Write
Read Only
Read/Clear
Read/Write
136
137
138
139
139
x‘5D’ to x‘5F’
x‘60’ and x‘61’
x‘62’ and x‘63’
prsq-64g.01.fm
December 20, 2001
Register Descriptions
Page 65 of 199
IBM [ IBM ]
