IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
5.1.8 BIST Select Register
This register, along with the BIST Data Register (page 70), provides indirect read/write access to the internal
PRPG and MISR registers.
Write access to an internal PRPG or MISR register requires two SHI commands:
1. Write the BIST register select field of the BIST Select Register with the value specifying which internal
PRPG or MISR register is to be accessed.
2. Write the BIST Data Register with the value desired for the internal PRPG or MISR register specified in
step 1. The internal PRPG or MISR register is loaded.
Read access to an internal PRPG or MISR register requires two SHI commands:
1. Write the BIST register select field in the BIST Select Register with the value specifying which internal
PRPG or MISR register is to be accessed.
2. Read the BIST Data Register. The value for the internal PRPG or MISR register specified in step 1 is
returned.
Address
x‘08’
Access Type
Reset Value
Read/Write
‘0000 0000 0000 0000 0000 0000 0000 0000’
Shift
Speed
Reserved
Scan Chain Length
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Bit(s)
0
Field Name
Reserved
Description
Reserved.
Specifies the BIST register:
000
001
010
011
PRPG0
PRPG1
PRPG2
PRPG3
100
101
110
111
MISR0
MISR1
MISR2
MISR3
1:3
4:5
6:7
BIST Register Select
Reserved
Reserved.
Defines the delay between the A and B clock pulses while shifting occurs during the BIST:
00
01
10
11
8 ns
16 ns
24 ns
32 ns
Shift Speed
8:19
Reserved
Reserved.
20:31
Scan Chain Length
Specifies the scan chain length.
prsq-64g.01.fm
December 20, 2001
Register Descriptions
Page 71 of 199
IBM [ IBM ]
